Template:Infobox CPU architecture/doc

This template is for CPU instruction set architectures.

Description
All fields are optional.

Parameters
All parameters are optional.
 * name: Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
 * designer: Designer of the architecture
 * bits: Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
 * introduced: Year introduced
 * version: Version/revision of architecture/ISA
 * design: Design strategy, e.g. RISC, CISC
 * type: Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
 * encoding: Instruction set encoding, e.g. Fixed or Variable
 * branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch
 * endianness: Byte ordering, e.g. Little, Big, Bi
 * page size: Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
 * extensions: ISA extensions, e.g. MMX, SSE, AltiVec
 * open: Is the architecture open or not? (as in free or proprietary)
 * predecessor: Earlier architecture(s) this one is based on, if it has a separate page
 * successor: Later architecture(s) based primarily on this one, if it has a separate page


 * registers: Number and size of processor registers
 * gpr: Number of general-purpose registers (and size, if not indicated by bits=)
 * fpr: Number of floating-point registers (and size, if not indicated by bits=)
 * vpr: Number of vector registers (and size, if not indicated by bits=)